Structural devices
Structural devices

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Structural devices

7.4.7 Deposition of patterned films: lift-off and damascene

We have assumed throughout this section that the deposited film will cover the entire wafer surface and that its patterning will be performed by subsequent lithography and etching steps. However, some materials, most notably copper, can be very difficult to remove with micrometre-scale precision or better, making this sequence extremely difficult. Since copper, with its high electrical conductivity and good chemical properties, is increasingly used in microelectronic device fabrication, another way to create a patterned film had to be found.

In fact, two quite different methods are used. The easier method is lift-off, which begins with photolithographically creating a stencil from photoresist. A second, softer layer of resist is exposed to give the holes a small overhang. Metal deposition is by evaporation or PVD, optimised for low step coverage so that the islands deposited at the base of the holes are not connected to the bulk film on top of the photoresist. When the resist is later dissolved, the metal film peels away and only the metal on the substrate remains.

Smaller features, as in the most advanced modern CMOS (complementary metal-oxide-semiconductor) architectures, require the more difficult damascene method. A dielectric layer, such as CVD SiO2, is deposited and patterned by etching in the usual way. Copper is then deposited over the top, filling all the holes and being sure to leave no voids. This copper is then ground away in a process of chemical mechanical polishing (CMP) until the top of the dielectric layer is exposed and the pattern, in the copper filling the gaps, emerges. In the most advanced logic chips, with transistor-gate dimensions below 100 nm, oxide dielectric is now being replaced with more delicate organosilicate insulators, chosen for the low dielectric constant that reduces capacitances and allows faster device operation. Unfortunately, these materials are mechanically soft and friable and the CMP step is far from straightforward.

SAQ 16

Distinguish between the deposition requirements for a low-melting-point metal and a high-melting-point dielectric oxide.


Metals can be deposited using techniques such as electroplating or evaporation. An insulating dielectric (and inparticular a high-melting-point one) can prove more difficult to deposit. Techniques suitable for these insulating layers are spin-on reactive PVD (with RF bias) or CVD.


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